Last time, we explained transmission line theory and the physics of reflection and termination. In this article, which is FC39, we will cover impedance design. We will explain the practical aspects of how to actually calculate the "characteristic impedance" that has been repeatedly mentioned in the PCB Design series, and how to reflect it in PCB design.
Reconfirming the reasons why characteristic impedance design is necessary
As explained last time, characteristic impedance Z0 is an essential parameter determined solely by the cross-sectional structure of the wiring. We will reorganize the reasons for managing this appropriately in FC design.
Prevention of signal reflection (detailed last time) is the most direct reason. If the characteristic impedance of the wiring does not match the expected values of the driver and receiver (often 50Ω, 90Ω for differential signals, etc.), reflections will occur as discontinuities in the transmission line.
Compliance with standards is also a practical reason for FC design. Communication standards such as USB, CAN, and Ethernet clearly specify the characteristic impedance of wiring, and failure to comply with these will cause problems with interoperability and certification acquisition.
There is also an indirect contribution to EMI suppression. If the characteristic impedance deviates from the design value, it also affects the return current path (FC25, FC36), which can result in degraded EMI characteristics.
Calculation formula for microstrip lines
We will reorganize the approximation formula for microstrip lines introduced last time into a form that can be used for practical design.
Calculation formula based on IPC-2141 (industry standard design guidelines):
Z0 = (87/√(εr+1.41)) × ln(5.98h/(0.8w+t))
Let's confirm the practical meaning of each parameter.
εr (relative permittivity) is determined by the board material. It is about 4.3 to 4.5 for standard FR-4, but it has frequency dependence and may drop to about 4.0 to 4.2 for higher-speed signals (GHz band) (frequency dispersion of permittivity).
h (dielectric thickness) is a parameter determined by the stack-up design explained in FC31. The distance between Layer 1 (signal) and Layer 2 (GND) corresponds to this.
w (trace width) is the main parameter adjusted by the designer. Increasing the trace width increases capacitance and decreases characteristic impedance.
t (copper foil thickness) is determined by the board manufacturer's standard specifications (usually 1oz=35µm, 2oz=70µm).
From this formula, for a target Z0 (e.g., 50Ω), if εr and h are fixed by the board specifications, the trace width w is calculated in reverse.
Calculation formula for striplines
We will also organize the calculation formula for the stripline structure (inner layer wiring, reference planes on both sides) explained in FC36.
Approximation formula for symmetric striplines (when the distances to the upper and lower reference planes are equal):
Z0 = (60/√εr) × ln(4b/(0.67π×w×(0.8+t/w)))
b is the total distance between the top and bottom planes, w is the trace width, and t is the copper foil thickness.
Unlike microstrip lines, striplines have the trace completely embedded within the dielectric, so they are more directly affected by the dielectric constant. Even with the same trace width, striplines generally tend to have lower impedance than microstrip lines (because the electromagnetic waves are completely confined within the dielectric, the effective dielectric constant approaches εr itself).
Calculation of Differential Impedance
We will organize the differential impedance calculation formulas for differential pairs, which were covered in FC33, in more detail.
Approximation formula for differential microstrip lines:
Zdiff ≈ 2×Z0×(1 - 0.48×e^(-0.96×s/h))
Z0 is the single-ended impedance calculated as an individual trace, s is the gap between the P and N traces, and h is the dielectric thickness.
From this formula, as the gap s increases (approaching loose coupling), Zdiff approaches 2×Z0 (because the coupling weakens and it approaches an independent trace). Conversely, as s decreases (tight coupling), Zdiff becomes smaller than 2×Z0.
The practical design process is an iterative calculation where, for a target differential impedance (USB 90Ω, CAN equivalent, etc.), you first tentatively determine the single-ended trace width w, and then adjust the gap s while considering the coupling effect. Since manual calculation is cumbersome, utilizing the dedicated tools introduced in the next section is practical for real-world work.
Practical Application of Impedance Calculation Tools
We will introduce impedance calculation tools actually used in FC design.
Saturn PCB Toolkit is an industry-standard tool available for free, supporting impedance calculations for various structures such as microstrips, striplines, and differential pairs. By inputting stack-up parameters (dielectric thickness, dielectric constant, copper foil thickness), you can back-calculate the required trace width and gap from the target impedance.
KiCad's built-in calculation feature, the "PCB Calculator" tool within the PCB editor, allows for similar microstrip and differential pair calculations. By linking it with the stack-up settings during design, you can achieve a seamless design flow.
Calculation tools provided by PCB manufacturers are also practical. PCB manufacturers such as JLCPCB and PCBWay provide impedance calculation tools on their websites based on their own standard stack-up specifications, allowing you to obtain more practical values that account for manufacturing tolerances.
Electromagnetic field solvers (such as Ansys HFSS mentioned previously) allow for more accurate calculations than approximation formulas, but for the scale of FC design, approximation calculation tools like Saturn PCB Toolkit usually provide sufficiently practical accuracy.
Practical Example—Impedance Design for USB Differential Pairs
We will demonstrate the impedance design process using specific numerical examples.
Design conditions: 4-layer board, FR-4 (εr=4.3), layer 1-2 spacing h=0.15mm, copper foil thickness t=35µm (1oz), target differential impedance 90Ω (USB 2.0)
Step 1: Tentative calculation of single-ended impedance
Assuming trace width w=0.2mm, substitute into the microstrip line formula:
Z0 ≈ (87/√(4.3+1.41)) × ln(5.98×0.15/(0.8×0.2+0.035))
≈ (87/2.39) × ln(0.897/0.195)
≈ 36.4 × ln(4.6)
≈ 36.4 × 1.526
≈ 55.6Ω
Step 2: Calculating Differential Impedance
Assuming a gap s=0.2mm:
Zdiff ≈ 2×55.6×(1-0.48×e^(-0.96×0.2/0.15))
≈ 111.2×(1-0.48×e^(-1.28))
≈ 111.2×(1-0.48×0.278)
≈ 111.2×0.867
≈ 96.4Ω
Step 3: Fine-tuning
Since 96.4Ω is slightly higher than the 90Ω target, recalculate by narrowing the gap s (to increase coupling) or widening the trace width w (to lower Z0). In practice, tools perform this iterative calculation automatically and instantly suggest a combination of trace width and gap that converges to the target value.
Manufacturing Tolerances and Impedance Allowances
Differences between calculated values and the actual characteristic impedance after manufacturing occur due to manufacturing tolerances.
Major error factors include manufacturing tolerances in trace width (etching errors, typically around ±10–20%), dielectric thickness errors (variations during prepreg lamination), and dielectric constant errors (lot-to-lot variations in PCB material).
Regarding tolerance specifications, many PCB manufacturers offer an "impedance control" service that guarantees a tolerance of approximately ±10% for specified impedance values. While this service involves additional costs, it is recommended for designs requiring compliance with standards such as USB or CAN.
In standard manufacturing without specified impedance control, larger errors (±20% or more) may occur. Therefore, for signals requiring strict impedance management (USB, high-speed differential pairs), it is practically important to explicitly specify impedance control when placing a manufacturing order.
Priority Judgment in FC Design—Which Signals Require Impedance Design
Applying strict impedance calculations to every trace in an FC design is inefficient. Here is a summary of the criteria for determining priority.
Signals requiring strict management include USB (D+/D-), CAN (CANH/CANL), high-speed SPI (several tens of MHz or higher, especially for long traces), and Ethernet (if applicable). These either have characteristic impedance defined by standards or exhibit significant reflection effects due to their high speed.
Signals that can be handled by rules of thumb include low-speed I2C, UART, and GPIO control signals. If the trace length is short (within typical distances on an FC board, a few cm) and the signal speed is low (a few MHz or less), ensuring the continuity of the reference plane, as explained in FC25 and FC36, is more important in practice than strict impedance calculation.
Signals requiring intermediate judgment include IMU SPI (clock in the tens of MHz). If the trace length is short, rules of thumb (waveform shaping with damping resistors) are often sufficient, but if the board is large and the traces are long, consider impedance calculation and TDR verification (see previous section).
Impedance Specification Workflow in KiCad
Here is a summary of the practical workflow in actual PCB design tools.
Integration with stack-up settings begins by reflecting the Physical Stackup information (dielectric thickness, dielectric constant) set in FC31 into the PCB Calculator tool.
Rule setting in net classes involves setting the trace width and gap calculated for specific nets (USB_DP, USB_DM, etc.) as design rules, so that these rules are automatically applied during routing.
Utilizing the differential pair routing tool, as introduced in FC33, involves performing actual routing using KiCad's differential pair routing mode based on the pre-calculated width and gap settings.
Verification via DRC involves checking for violations of the set width and gap rules after routing is complete. However, as discussed in FC30, note that DRC only confirms whether "routing follows the set rules," and whether "that trace width and gap truly achieve the target impedance" depends on prior verification using calculation tools.
Summary
Characteristic impedance design starts with the calculation formulas for microstrip lines and striplines. Using the Saturn PCB Toolkit or the built-in calculation functions in KiCad, we practically determine the trace width and gap required to achieve the target impedance (USB 90Ω, CAN, etc.). Considering manufacturing tolerances, we consider using impedance control services for signals that require standards compliance. It is practical to prioritize resources for signals where the effects of reflection are significant, such as USB, CAN, and high-speed SPI, rather than applying strict calculations to every trace in an FC design. With this, the theoretical core of the PCB Design series (return current, transmission lines, impedance) is complete. In the next installment, FC40, we will explain the practical development flow for linking KiCad and hwdef—PCB design data and ArduPilot's hwdef.dat—which will be the final installment of the PCB Design series.