Last time, we explained circuit description in the frequency domain using S-parameters. In this article, which is FC38, we will cover transmission lines. We will discard the simplification that has been an implicit assumption until now—that 'signals travel through wiring instantaneously'—and systematically explain the theory of reflection and termination based on the physics that signals are 'waves' propagating at a finite speed.
Why is it necessary to treat wiring as a 'transmission line'?
In low-frequency circuits, wiring is treated simply as a conductor (a connection with zero resistance). However, with high-frequency signals or high-speed digital signals, the wiring itself begins to exhibit its own electrical behavior depending on the relationship between the wiring length and the signal wavelength.
The criterion for whether to treat it as a transmission line is the ratio of the wiring length to the signal wavelength. As a rule of thumb, when the wiring length exceeds 1/10 of the signal wavelength, the effects of the transmission line (reflection, delay) can no longer be ignored.
Let's verify this with specific numbers. The signal propagation speed on an FR-4 board, assuming a dielectric constant εr ≈ 4.3, is:
v = c / √εr ≈ 3×10⁸ / 2.07 ≈ 1.45×10⁸ m/s
The wavelength of a 100MHz signal is:
λ = v / f ≈ 1.45×10⁸ / 100×10⁶ ≈ 1.45m
In this case, if the wiring length exceeds 14.5cm (1/10 of the wavelength), it is necessary to consider transmission line effects. For the clock of an STM32H7 (480MHz) or high-speed SPI (tens of MHz), the wavelength is shorter, so even wiring of a few centimeters on an FC board may need to be treated as a transmission line.
Distributed Constant Circuit Model
A transmission line is modeled as a Distributed Element Circuit.
A lumped constant circuit (the model implicitly used in many discussions so far) assumes that resistance, inductance, and capacitance are concentrated at specific points in the circuit. The ESL of the decoupling capacitor in FC23 and the inductance of the via in FC32 were approximations using this lumped constant model.
A distributed constant circuit considers resistance R, inductance L, conductance G, and capacitance C to be distributed per unit length of the wiring. For every infinitesimal section dx of the wiring, these elements are represented as an infinite ladder circuit connected in series and parallel.
From this distributed constant model, a wave equation is derived in which voltage and current propagate as waves along the wiring:
∂²V/∂x² = LC × ∂²V/∂t²
The solution to this equation takes the form of a voltage wave (traveling wave) that propagates at a constant speed along the wiring.
Physical Derivation of Characteristic Impedance
The characteristic impedance Z0, which is the most important parameter of a transmission line, is derived from this distributed constant model.
The characteristic impedance in a lossless line (approximated as R=0, G=0, which is a valid approximation at high frequencies) is:
Z0 = √(L/C)
L is the inductance per unit length, and C is the capacitance per unit length.
An important property indicated by this formula is that the characteristic impedance does not depend on the length of the wiring. Z0 is determined solely by the cross-sectional structure of the wiring (width, distance to the reference plane, and dielectric constant), and no matter how long the wiring is, its characteristics per unit length remain constant.
Approximate formula for the characteristic impedance of a microstrip line (structure explained in FC36):
Z0 ≈ (87/√(εr+1.41)) × ln(5.98h/(0.8w+t))
h is the dielectric thickness, w is the wiring width, and t is the copper foil thickness. From this formula, it can be seen that Z0 increases by making the wiring thinner (decreasing w) or by making the dielectric thicker (increasing h). We will handle this design formula more practically in FC39.
Incident Waves and Reflected Waves
A signal traveling along a transmission line propagates from the transmitter to the load as an incident wave. If the load impedance does not match the characteristic impedance of the line, a portion of the energy returns to the transmitter as a reflected wave.
This is the same phenomenon as S11 in the S-parameters explained previously. While S-parameters provide a description in the frequency domain, transmission line theory provides a description in the time domain (when and where waves reflect).
The reflection coefficient Γ is expressed by the same formula as before:
Γ = (ZL - Z0) / (ZL + Z0)
When ZL > Z0 (close to open), Γ takes a positive value, and the reflected wave returns with the same polarity as the incident wave.
When ZL < Z0 (close to short), Γ takes a negative value, and the reflected wave returns with the opposite polarity to the incident wave.
When ZL = Z0 (matched), Γ=0 and no reflection occurs. This is the physical meaning of 'matching'.
Signal Quality Issues Caused by Reflections
Various signal quality issues arise when reflected waves overlap with the original incident wave.
Ringing is a phenomenon where the voltage oscillates and settles after a signal edge. If there is impedance mismatch at both the signal source and the load, the reflected wave reflects repeatedly at both ends (multiple reflections), causing this oscillation.
Overshoot and undershoot are phenomena where the signal temporarily exceeds the High/Low levels, which can cause failure if the IC's absolute maximum ratings are exceeded.
Uncertainty in signal delay also occurs. Due to the superposition of reflected waves, the timing at which the signal crosses the threshold for High/Low determination on the receiving side may deviate from the ideal waveform. This causes a reduction in the timing margin of digital signals.
These phenomena are physical phenomena (LC resonance, reflection) similar to the ringing during dead time explained in ESC15 or the false triggering due to the Miller effect in ESC17, appearing in the different context of transmission lines.
Types of Termination Methods
There are several methods for termination to suppress reflections.
Series termination is a method where a resistor is inserted in series at the output of the signal source, corresponding to the difference between the characteristic impedance of the line and the input impedance of the load. Since the output impedance of many digital ICs is low (a few ohms to several tens of ohms), the difference from the characteristic impedance (e.g., 50 ohms) is compensated for by the resistor.
The advantage of series termination is that there is no current consumption in the steady state (no current flows when the signal is stable at High or Low). The disadvantage is that reflections at the load side (a state close to an open circuit at the receiving end) still remain, so it is not a complete solution, especially in bus configurations with multiple loads.
Parallel termination is a method where a resistor with the same value as the characteristic impedance is connected to VCC or GND at the load side (receiving end). It directly suppresses reflections at the load side.
The disadvantage of parallel termination is that steady-state current consumption occurs. If a 3.3V signal is passed through a 50-ohm termination, a current of 66mA will flow constantly, which causes issues with increased power consumption and heat generation. While widely used in high-speed buses, careful application is required in FC designs where low power consumption is demanded.
AC termination is a method that adds a capacitor in series with the parallel termination resistor, eliminating steady-state current consumption while suppressing only transient reflections. It is a compromise that combines some of the advantages of both series and parallel termination.
Differential termination is a method specialized for the termination of differential pairs explained in FC33, where a resistor matched to the differential impedance is connected between the P and N lines. The 120-ohm termination resistor of the CAN bus (explained earlier in the series) is a representative example of this.
Practical Application of Termination in FC Design
We will organize the application of termination for various signals on FC boards.
For SPI buses (connections to IMUs, barometers, etc.), the wiring length is often short (within a few centimeters), and in many cases, there is no practical problem even without termination. However, if the wiring is long (e.g., wiring from one end of the board to the other) or the clock frequency is high, a damping resistor (explained in the previous series, a series resistor of about 22 to 33 ohms) functions as a de facto simple series termination.
For the CAN bus (see the previous series), a 120-ohm termination resistor is required at both ends of the bus as part of the standard. This is a typical example of differential termination and is a strict requirement based on transmission line theory.
For the USB bus (D+/D-), termination resistors are often built into the driver side within the standard, so PCB designers usually do not need to design additional termination resistors (reconfirming the content mentioned in FC33).
For clock signals (wiring from an MCU's external crystal oscillator, etc.), termination is unnecessary if the wiring is short, but when distributing a clock to multiple ICs, termination design (or ingenuity in the distribution method, or the use of a clock buffer IC) that considers reflections at each branch destination may be necessary.
Placement of Termination Resistors in Implementation
We will organize the design considerations when actually placing termination resistors.
Series termination resistors should be placed as close as possible to the pins of the signal source (driver IC). By placing the termination resistor between the wiring and the driver, the effect of compensating for the driver's output impedance is maximized.
Parallel termination resistors are ideally placed near the load (receiving IC), but if multiple loads are distributed on the bus, it is common to place them at the very end of the bus (the physically farthest load).
The placement of termination resistors is related to the via stub problem explained in FC32. If a via is included in the wiring path to the termination resistor, the additional reflection caused by the stub may partially impair the termination effect, so simplifying the wiring path (minimizing layer changes) is a desirable design.
Transmission Line Theory and TDR Measurement
TDR (Time Domain Reflectometry), which we touched upon last time, is a measurement method that practically applies transmission line theory.
TDR visualizes impedance changes on a line as positional information by injecting a step-like signal into the line and observing the temporal return of the reflected wave. From the timing of the reflected wave's return, the distance to the mismatch point can be calculated back from the signal propagation speed.
Distance resolution depends on the TDR step rise time; with high-speed TDR (rise time of several tens of ps), it is possible to identify mismatch points on a PCB in units of several millimeters.
Its application in FC design is particularly effective for post-prototype failure analysis (identifying the cause when problems occur with specific high-speed signals). The effects of via stubs explained in FC32 and the impedance mismatch points of differential pairs in FC33 can be directly observed through TDR measurement of the actual device.
Summary
Transmission line theory begins with the recognition that when wiring length exceeds 1/10 of the signal wavelength, the wiring must be treated as a distributed constant circuit. Characteristic impedance Z0=√(L/C) is an essential parameter determined solely by the cross-sectional structure of the wiring, and the mismatch with load impedance is quantified as the reflection coefficient Γ. Reflections cause signal quality issues such as ringing and overshoot, which are addressed through multiple termination methods: series termination, parallel termination, AC termination, and differential termination. The 120Ω termination of the CAN bus is a representative example of differential termination and is the clearest practical application of transmission line theory in FC design. In the next installment, FC39, we will explain impedance—the design calculation of characteristic impedance and practical PCB design using tools.