In the previous article, we explained crosstalk suppression techniques. In this article, FC35, we will cover power planes. We will reconstruct the decoupling capacitors (FC23), power trees (FC21), and stack-ups (FC31), which we have treated individually until now, from the integrated perspective of a PDN (Power Distribution Network), and explain the often-overlooked issue of plane resonance.
The Concept of PDN
A PDN (Power Distribution Network) is a design philosophy that views the entire electrical path from the power source (VBAT or regulator) to the IC's power pins as a single system.
The DC-DC converters (FC22), decoupling capacitors (FC23), power planes (this article), and vias (FC32) that we have treated individually in previous articles are all components of a single system called the PDN. The goal of PDN design is to be able to supply the instantaneous current required by the IC at low impedance across all frequency bands.
The concept of "Target Impedance" introduced in FC23 serves as the metric for the entire PDN design:
Z_target = ΔV / ΔI
The goal of PDN design is to satisfy this target impedance across the entire frequency band of the PDN, from DC (0 Hz) to high frequencies (several hundred MHz).
PDN Impedance Curve—The Main Players by Frequency Band
The actual impedance of a PDN is dominated by different elements depending on the frequency.
In the low-frequency range (DC to several tens of kHz), the output impedance of the power regulator (DC-DC, LDO) and the responsiveness of its feedback control are dominant. The transient response characteristics of the regulator (voltage fluctuation and recovery time during sudden load changes) determine the impedance in this band.
In the mid-frequency range (several tens of kHz to several MHz), bulk capacitors (explained in FC23, 10–100 µF electrolytic/polymer capacitors) primarily function.
In the mid-to-high frequency range (several MHz to several tens of MHz), medium-capacity MLCCs (1–10 µF) take the lead.
In the high-frequency range (several tens of MHz to several hundred MHz), small-capacity MLCCs (0.01–0.1 µF) and the ESL (see FC23) resulting from their placement are dominant.
In the ultra-high frequency range (several hundred MHz and above), the parallel-plate capacitor structure itself, formed by the power plane and GND plane which are the subject of this article, acts as decoupling.
Function of Power Planes as Parallel-Plate Capacitors
When a power plane and a GND plane are placed adjacent to each other (Pattern A explained in the FC31 stack-up, power-GND adjacent configuration), these two planes function as a giant parallel-plate capacitor.
Capacitance of a parallel-plate capacitor:
C_plane = ε0 × εr × A / d
ε0 is the permittivity of vacuum, εr is the relative permittivity of the board material (approx. 4.3 for FR-4), A is the overlapping area of the planes, and d is the distance between the planes.
Calculation example for a typical FC board (power plane area 1000 mm², inter-layer distance 0.15 mm):
C_plane = 8.85×10⁻¹² × 4.3 × 1000×10⁻⁶ / 0.15×10⁻³ ≈ 254pF
Although this is a relatively small capacitance of several hundred pF, this plane capacitor has the characteristic of extremely low ESL (equivalent series inductance). While the ESL of an MLCC is around 0.3 to 1nH, the ESL of a plane capacitor is overwhelmingly smaller, on the order of several tens of pH (picohenries), which pushes the SRF (self-resonant frequency) discussed in FC23 to a very high frequency (several hundred MHz to GHz).
For this reason, in the highest frequency bands (the band exceeding the SRF of individual decoupling capacitors), the power plane-GND plane structure itself functions as the final decoupling measure.
The Problem of Plane Resonance
While the power plane and GND plane pair functions as a parallel plate capacitor, it causes another problem called plane resonance under certain conditions.
Plane resonance is a phenomenon where signals reflect at the edges of the plane, forming standing waves. If you view the plane as a collection of transmission lines, there are inherent resonant frequencies corresponding to the dimensions of the plane.
The resonant frequency of a rectangular plane can be calculated from the plane's dimensions (length a, width b):
f_mn = (c / (2√εr)) × √((m/a)² + (n/b)²)
c is the speed of light, and m and n are the resonant mode orders (integers).
The lowest-order resonant modes (m=1, n=0 or m=0, n=1) are the most problematic, and in typical FC-sized power planes (several cm square), resonance can occur at frequencies around several hundred MHz to 1 GHz.
The reason plane resonance is a problem is that the impedance of the plane increases sharply (ideally approaching infinity) near the resonant frequency. This is similar to the phenomenon explained in FC23 where 'a capacitor behaves as an inductor once it exceeds its SRF,' but here, the entire plane acts as a resonant structure.
Impact of Plane Resonance
Let's summarize the specific impacts of plane resonance on FC design.
A local deterioration in power impedance means that the PDN impedance significantly exceeds the target value near the resonant frequency. If the IC requires current in this frequency band, voltage fluctuations (noise) will increase.
Increased radiated EMI also occurs. Plane resonance becomes a source of radiated EMI (see FC26–FC27) as electromagnetic waves leak from the plane edges to the outside. The entire plane acts as a large antenna.
Coincidence with the clock or its harmonics is the worst-case scenario. If the MCU clock frequency or its harmonics (explained in FC26) happen to match the plane resonant frequency, voltage fluctuations due to resonance are amplified, which can cause serious EMI problems.
This is why, when considering FC board size and component placement, it is necessary to perform additional checks not just for whether it is 'electrically correct,' but also for 'whether physical resonance occurs at problematic frequencies.'
Methods for Suppressing Plane Resonance
Let's summarize the design methods for suppressing plane resonance.
Strategic placement of decoupling capacitors is the most fundamental countermeasure. To absorb the energy of plane resonance with decoupling capacitors, capacitors that are effective in the frequency bands where resonance is expected (capacitance values with appropriate SRF) are distributed across the plane. The parallel placement of multiple capacitances (10µF+1µF+0.1µF+0.01µF) explained in FC23 also contributes to the suppression of plane resonance as a result.
Termination at the plane edge is a technique where resistors are placed at the edge of the plane to absorb reflected waves. It follows the same principle as the termination of transmission lines used in high-speed digital circuit design (detailed in FC38), but its application to two-dimensional plane structures is more complex. It is not very common in practical FC design and is a technique used in more advanced high-speed designs (such as server motherboards).
Plane shape optimization is a technique to avoid a single strong resonance mode and disperse it into multiple weaker resonances by intentionally making the plane dimensions asymmetrical or by dividing them into multiple smaller plane regions (while maintaining electrical connectivity).
Strategic placement of vias is also effective. By distributing the vias of decoupling capacitors that connect the power plane and GND plane evenly across the plane, the energy of the resonance modes is attenuated more effectively. This is also related to the discussion of via inductance explained in FC32, where the via placement pattern affects the characteristics of plane resonance.
Reality of Plane Resonance in Small FC Boards
We will perform a realistic evaluation of plane resonance in small boards like FC (typically a few centimeters square).
From the resonance frequency formula mentioned earlier, we estimate the lowest-order resonance mode for a typical FC size (a power plane of about 50mm x 50mm):
f_10 ≈ (3×10⁸ / (2×√4.3)) × (1/0.05) ≈ 1.45×10⁹ Hz ≈ 1.45GHz
In this calculation example, the lowest-order resonance is around 1.45GHz, which is relatively far from the main signal frequencies handled in FC design (MCU clock 480MHz, SPI tens of MHz, etc.). However, caution is required as the harmonics of these signals (the 3rd harmonic of 480MHz is 1.44GHz) may approach the resonance frequency.
As a practical judgment, serious plane resonance problems rarely manifest in small FC boards, but more careful consideration is required when the board size increases (such as in companion computer integrated boards) or when the frequency of the signals handled becomes higher (GHz-band high-speed interfaces).
Interaction Between Multiple Power Planes
As explained in FC31, in actual FC boards, multiple voltage rails (3.3V_MCU, 3.3V_SENSOR, 5V_MAIN, etc.) exist as divided plane regions within the same layer.
Each of these divided plane regions may have its own unique resonance characteristics. As the number of plane division boundaries (edges) increases, the complexity of the resonance modes also increases.
Crosstalk between power planes (a fusion of this article and the previous discussion on crosstalk) is also a phenomenon that should be considered. Noise propagation via capacitive coupling can occur between adjacent plane regions of different voltages. The 'independent separation of sensor power' explained in FC22 also has the aspect of protection against this type of inter-plane crosstalk.
Verification of PDN Design—Impedance Measurement and Simulation
We will organize the methods for verifying the design quality of the entire PDN.
Impedance measurement using a VNA (Vector Network Analyzer) is the most reliable method for directly measuring the frequency characteristics of a PDN. The impedance between the power pin and GND is measured over a wide band (several kHz to several GHz) to confirm whether the target impedance set in FC23 is met across the entire band.
PDN analysis-specific tools (Altium Designer PDN Analyzer, Ansys SIwave, etc.) simulate PDN impedance from design data (stack-up, component placement, capacitor values) to identify problematic frequency bands in advance. While the introduction cost may not be justified for the scale of FC design, it is worth the investment for industrial and high-reliability designs.
Sensor noise evaluation on the actual machine is the final confirmation of practicality, where we evaluate whether PDN design issues are affecting actual system performance using EKF innovation statistics or sensor noise floor measurements as explained in FC14.
Summary
A PDN (Power Distribution Network) is a system where multiple elements—regulators, bulk capacitors, MLCCs, and power planes—share the role of decoupling in different frequency bands. Power planes and GND planes act as parallel-plate capacitors to handle decoupling in the ultra-high frequency band, but they simultaneously have the inherent problem of plane resonance. Plane resonance often appears at relatively high frequencies (GHz band) in small boards like FC, and attention must be paid to its coincidence with the harmonics of the MCU clock. Strategic placement of decoupling capacitors is an integrated measure that contributes to both capacitive decoupling and plane resonance suppression. In the next issue, FC36, we will further explain the reference plane—the role of the reference plane in signal quality and EMI—by integrating the discussions so far.