In the previous article, we explained the stack-up configuration of a 4-layer board. In this article, which is FC32, we will cover via design. We touched on the importance of "GND stitching vias when changing layers" in FC25, but in this article, we will delve into the structure of the vias themselves, their impact on high-speed signals, and the specialized techniques to minimize these effects.
Basic Structure of a Via
A via is a through-hole that electrically connects different layers of a PCB. It is created by drilling a hole and plating the inner walls (electroplated copper) to provide conductivity.
A Through-hole Via is the most basic type of via that penetrates all layers of the board. It is the simplest and lowest-cost to manufacture, but even in a 4-layer board, it physically penetrates all layers (layers 1 to 4).
A Blind Via is a partial connection from a surface layer to an inner layer and does not penetrate to the opposite side. It is possible to create a configuration that connects only from layer 1 to layer 2.
A Buried Via connects only between inner layers and is not visible from the surface. This configuration connects, for example, only between layers 2 and 3.
In 4-layer boards, through-hole vias are standard, while blind and buried vias are adopted for more complex multilayer boards (8 layers or more) or when particularly high-density mounting is required. The cost can be several times that of a standard through-hole, so in FC design, through-hole vias are the basic choice unless there are special requirements.
Parasitic Inductance of Vias
The "parasitic inductance" that appeared repeatedly in ESC11–ESC18 and FC23 also exists in vias.
Approximate formula for via inductance:
L_via ≈ 5.08 × h × [ln(4h/d) + 1] (in nH, where h and d are in mils)
h is the length of the via (approximately equal to the board thickness), and d is the diameter of the via.
For a standard 4-layer board (thickness 1.6mm ≈ 63mil) with a via diameter of 0.3mm (≈ 12mil):
L_via ≈ 5.08 × 63 × [ln(4×63/12) + 1] ≈ 5.08 × 63 × [3.04+1] ≈ 1293 [pH × coefficient adjustment required]
Careful unit conversion is required, but as an approximation, an inductance of around 1nH exists in a typical via. In the discussion of decoupling capacitors in FC23, we showed an example of "5nH for 5mm of wiring," and it can be seen that the via itself has an inductance of a similar order.
This parasitic inductance has a non-negligible impact on high-speed signals. The shorter the signal rise time (the more high-frequency components it contains), the greater the impact of impedance discontinuity due to via inductance.
The Problem of Via Stubs
The biggest problem that through-hole vias pose to high-speed signals is the Via Stub.
A stub is the unused portion of a via that remains beyond the layer change (e.g., from layer 1 to layer 2) that the signal actually requires. When using a through-hole via to connect from layer 1 to layer 2 in a 4-layer board, the via physically penetrates to layers 3 and 4, so the part below layer 2 remains as an "extra unused conductor."
This stub acts like a resonant antenna. The resonant frequency corresponding to the stub length L:
f_resonance = c / (4 × L × √εr)
c is the speed of light, and εr is the relative permittivity of the board material (approximately 4.3 for FR-4).
For example, if a 1.6mm thick board has a layer 1-2 connection (required length approx. 0.2mm) and the section between layers 2-4 (approx. 1.4mm) remains as a stub:
f_resonance ≈ 3×10⁸ / (4×1.4×10⁻³×√4.3) ≈ 2.6×10¹⁰ Hz ≈ 26GHz
In this example, the frequency is very high at 26GHz, which often does not pose a direct problem for signals handled in FC designs (several hundred MHz or less). However, in designs handling higher-speed signals (USB 3.0, PCIe, etc., several GHz), stub resonance becomes a serious factor in signal degradation.
When handling companion computer connections for industrial FCs (high-speed USB, MIPI CSI, etc.), countermeasures for this stub problem are necessary.
Back-Drilling—Stub Removal
Back-drilling is a manufacturing technique that physically removes stubs.
After forming a standard through-hole via, the unnecessary portion beyond the point where the signal layer change is completed is removed from the back side using a drill again. This significantly shortens the stub length and pushes the resonance frequency up to a level that does not cause practical problems.
The manufacturing cost of back-drilling is higher than that of standard through-hole vias. Because it requires additional drilling steps and precise depth control, it is common for board manufacturing costs to include a premium of several tens of percent.
The decision to apply it in FC design is determined by the maximum frequency of the signals being handled. As mentioned above, back-drilling is usually unnecessary for the FC main unit, where signals of several hundred MHz or less are primary, but it is worth considering for expansion boards that handle high-speed companion computer interfaces (MIPI, PCIe, etc.) mounted on industrial FCs.
Via-in-Pad
Via-in-pad is a technology that places vias directly on IC pads (especially under BGA packages).
In standard designs, vias are placed at a position slightly away from the pad and connected to the pad with a short trace (tether). Via-in-pad eliminates this tether and places the via directly under the pad, making the trace length effectively zero.
The advantage is that it minimizes the 'inductance increase due to trace length' discussed in the decoupling capacitor placement section of FC23. By creating a connection to the decoupling capacitor via a via-in-pad directly under the power pin, decoupling is achieved via the shortest path.
As a manufacturing challenge, via-in-pad cannot usually be used as is. Solder would flow into the via hole, reducing the reliability of the solder joint. To solve this, additional steps are required: via filling (filling the via hole with conductive or non-conductive resin) and cap plating (flattening the surface after filling and covering it with plating).
Regarding the impact on cost, the combination of via-in-pad + via fill + cap plating is significantly more expensive than standard vias. In high-density pin arrangements for BGA package MCUs (such as the STM32H7), routing may be difficult without via-in-pad, so adoption is decided based on the balance between necessity and cost.
Microvias and HDI Boards
When higher-density mounting is required, HDI (High Density Interconnect) boards using microvias are an option.
Microvias are very small diameter (0.1mm or less) vias formed by laser drilling, mainly used as blind vias between adjacent layers (e.g., between layers 1-2). They are significantly smaller than mechanical drill through-hole vias, and their parasitic inductance is also smaller.
Stacked Vias are a structure where multiple microvias are stacked across layers to achieve more complex interlayer connections.
HDI boards are increasingly being used to accommodate the fine pitch of BGA packages (such as high-pin-count MCUs like the STM32H7). While they enable high-density routing that cannot be achieved with standard 4-layer FR-4 boards, manufacturing costs increase several-fold.
Application in FC design is considered for ultra-compact FCs (such as tiny boards for racing drones) or when using high-performance MCUs with many pins (BGA, 0.4mm pitch or less). For standard industrial FCs, a 4-layer board with standard through-hole vias is often sufficient, and HDI is decided based on a trade-off with cost.
Via Placement and Return Current—Practical Placement Rules
We will organize the return current principles explained in FC25 into concrete via placement rules.
The distance between signal vias and GND stitching vias is generally recommended to be within 1 to 2 mm. If they are further apart, the effect of increased loop area due to the detour of the return current becomes significant.
When changing layers for a differential pair, place GND stitching vias near the middle of the two signal vias or on both sides. For differential pairs, it is ideal to consider both common-mode and differential-mode currents and place multiple GND vias to surround the entire pair.
Via sharing in high-density placement: In areas where multiple signal vias are concentrated (such as directly under a BGA package), there may not be enough space to place a dedicated GND stitching via for each signal via. In this case, strategically place GND vias that can be shared by multiple adjacent signal vias, and design them so that the distance from each signal is within the allowable range.
Decoupling placement across power planes: When a signal crosses a power plane split as explained in FC31, place a GND-to-power decoupling capacitor near the signal via (within a few mm) so that it functions as a path for the return current to travel.
Relationship between Via Design and DRC
The limitations of DRC explained in FC30 also apply to via design.
While DRC reliably checks the geometric correctness of vias (diameter, annular ring, drill size manufacturability), electrical and physical evaluations such as via stub resonant frequency and the validity of GND stitching via placement are outside the scope of standard DRC.
As an application of custom rules, tools like KiCad may allow you to define a custom rule that "a GND via must exist within a certain distance from a signal via of a specific net." This allows for partial automated checking of via placement validity as an example of the automation extensions explained in FC30.
Confirmation in 3D view: For complex via placement (especially around BGA packages), visually checking the actual placement density and the distribution of GND stitching vias in the 3D view remains the most reliable verification method.
Summary
Vias have two physical effects on signals: parasitic inductance (typically around 1nH) and stub resonance. The stub problem becomes significant for high-speed signals in the multi-GHz band and is addressed with back-drilling, but it is often not a major issue at the normal signal speeds of an FC main unit. Via-in-pad achieves zero-length decoupling connections but comes with the additional cost of via filling and cap plating. The placement of GND stitching vias (within 1 to 2 mm of signal vias) is the most concrete design task for practicing the return current principle of FC25, and since it cannot be evaluated by DRC, visual and 3D view confirmation remains important. In the next issue, FC33, we will explain differential pairs—length matching, coupling, and impedance management in differential signal routing such as CAN and USB.