Last time, we explained the limitations of DRC and the necessity of human review. This article, which is FC31 in the PCB Design series, covers 4-layer PCB design. We will explain in detail how to realize the principle of a 'GND plane directly below the signal layer,' which has been a premise in the Hardware Design series so far, as an actual stack-up configuration.
Why is a 4-layer PCB the standard?
With a 2-layer PCB (top and bottom only), it is necessary to share signal wiring and GND/power on the same layer, making it structurally difficult to realize the 'continuous GND plane' principle (FC24, FC25) that has been repeatedly emphasized in this series.
A 4-layer PCB can realize a basic configuration that can secure a return current path, such as 'Signal-GND-Power-Signal' or 'Signal-GND-GND-Signal,' with the minimum number of layers. As a balance point for cost, complexity, and performance in FC design, the 4-layer PCB has become the industry standard.
PCBs with 6 or more layers are used for more complex signals (high-speed digital, multiple differential pairs) or when there are stricter EMI requirements, but they increase cost and manufacturing lead time. In FC design, 4 layers is the standard solution that achieves 'sufficient performance at a realistic cost.'
Basic stack-up patterns
We will organize the typical stack-up configurations for a 4-layer PCB.
Pattern A (Signal-GND-Power-Signal) is the most standard configuration.
Layer 1 (Top): Signal layer (component mounting side)
Layer 2: GND plane
Layer 3: Power plane
Layer 4 (Bottom): Signal layer
The advantage of this configuration is that the signal on Layer 1 has a low-impedance return path relative to Layer 2 (GND), and the signal on Layer 4 has a similar path relative to Layer 3 (power plane, AC-wise GND via decoupling). The principle explained in FC25, 'a power plane also functions as a return path if there is appropriate decoupling,' is utilized here.
Pattern B (Signal-GND-GND-Signal) is used when there are stricter EMI requirements.
Layer 1: Signal layer
Layer 2: GND plane
Layer 3: GND plane (connected to Layer 2 with many vias)
Layer 4: Signal layer
Since both signal layers face a GND plane directly, it realizes the lowest impedance return path. However, because the power plane does not have a dedicated layer, power wiring must be done on the signal layer, which has the trade-off that the impedance of power distribution becomes somewhat higher.
Pattern C (Signal-Power-GND-Signal) is a configuration where the power and GND of Pattern A are swapped, and it may be chosen for specific IC placements (e.g., when an IC that uses a lot of power is on the Layer 1 side).
Practical stack-up for STM32H7-based FC
As a typical example of FC design, we will specifically consider the stack-up design of an FC that uses an STM32H7 as the main MCU.
On Layer 1 (Top, component side), we place the main ICs such as the MCU, IMU, compass, and barometer, as well as decoupling capacitors and connectors. High-speed signals (SPI, USB, etc.) are also mainly routed on this layer.
Layer 2 is a GND plane, maintaining continuity directly below the signal layer. The principle of 'avoiding unnecessary splits' explained in FC24 is most important in the design of this layer.
Layer 3 is often used as a power plane, with multiple voltage rails such as 3.3V_MCU, 3.3V_SENSOR, and 5V_MAIN split and placed. Unlike splitting a GND plane, splitting a power plane is essential because different voltages must be physically separated. However, as explained in FC25, if a signal changes layers across these power plane splits, a design that secures a return current path with sufficient decoupling capacitors is necessary.
Layer 4 (Bottom) is used for DC-DC converters, some connectors, and additional signal wiring when wiring becomes congested.
Design of Board Thickness and Layer Spacing
The physical thickness configuration of the stack-up also affects signal quality.
While 1.6mm is the industry standard for total thickness of a 4-layer board, 1.0mm to 1.2mm is sometimes chosen in FC designs for weight reduction.
Layer spacing (dielectric thickness) directly affects characteristic impedance (detailed in FC39). The narrower the spacing between layers 1 and 2 (typically 0.1 to 0.2mm), the stronger the coupling between the signal and GND, and the smaller the return current loop area.
The core and prepreg configuration consists of a core material (glass epoxy such as FR-4) sandwiching the two inner layers (GND and power), combined with prepreg to add the outer layers. There is a manufacturing constraint where the thickness between layers 2 and 3 (GND-power) is fixed by the core material, while the spacing between layers 1-2 and 3-4 can be adjusted using prepreg.
As a problem with asymmetric stack-ups, if the layer configuration is not symmetric between the top and bottom, board warpage is more likely to occur. Even with small boards like FC, warpage during reflow can cause soldering defects for BGA packages (such as MCUs), so stack-up design that considers symmetry is recommended.
Layer Placement Strategy for High-Speed Signals
Based on the principles of return current explained in FC25, we will organize a design strategy for assigning the optimal layer for each type of signal.
Highest-speed signals (SPI high-speed clock, USB HS, SDMMC) should be placed on layer 1 (directly above GND) whenever possible, minimizing layer changes. If a layer change is unavoidable, always include the GND stitching vias explained in FC25.
Medium-speed signals (UART, I2C, CAN) should be placed on either layer 1 or layer 4 to ensure good coupling with the GND plane.
Low-speed/static signals (LED control, GPIO, etc.) have high routing flexibility and play a role in relieving congestion on layer 1 by utilizing layer 4 or gaps in the inner layers.
For differential pair signals (CAN, USB), as explained in the previous series (Differential Signals, CMRR), it is essential to always keep the two wires of the pair on the same layer and the same reference plane. When changing layers, move the entire pair together and place GND stitching vias near both signal vias (detailed in FC33).
Power Plane Split Design
Split design for layer 3 (power plane) requires different considerations than splitting the GND plane.
Splitting the power plane is electrically essential. Different voltages such as 3.3V_MCU, 3.3V_SENSOR, and 5V_MAIN must exist as physically separated plane regions. The independent separation of power systems (separation of LDOs for MCU and sensors) explained in FC22 is embodied on the PCB in the form of this power plane splitting.
In the boundary design of the split, ensure sufficient clearance (insulation distance) between different voltage planes, and design the floorplan so that signal traces do not unnecessarily cross this boundary. As explained in FC25, if a signal changes layers across different voltage regions of the power plane, place dense decoupling capacitors near the boundary to ensure a path for the return current.
Power plane area allocation is performed according to the current capacity requirements of each voltage rail. By allocating a large area to 5V_MAIN, which carries high current, and the minimum necessary area to sensor-related power supplies with low current, board space is used efficiently.
Layer Strategy in Mixed-Signal Regions
We will organize special considerations for analog/mixed-signal regions such as GNSS, IMU, and compass.
Around these sensors, we will reflect in the layer design the guideline explained in FC24: 'In principle, avoid splitting analog GND and digital GND, but follow the recommendations in the datasheet for mixed-signal ICs such as ADCs.'
In many cases, this is achieved through "spatial separation without plane splitting," where the analog components of the sensor are physically placed away from the digital circuits on Layer 1, while keeping Layer 2 (GND) completely continuous.
As a special consideration for GNSS, particular attention must be paid to the routing layer from the antenna port to the GNSS IC for characteristic impedance management of the antenna feed line (detailed in FC39). In many designs, routing is performed on Layer 1 (top), and a microstrip line structure (detailed in FC38) is formed in combination with the continuous GND plane on Layer 2.
Tools and Workflow for Stackup Design
We will organize the practical steps for defining a stackup in actual PCB design.
Stackup settings in KiCad are defined in the Physical Stackup tab of the Board Setup screen, where the material, thickness, and copper thickness of each layer are specified. By referring to the standard stackup specifications provided by PCB manufacturers (such as JLCPCB, PCBWay, etc.) and configuring accordingly, you can achieve predictable characteristic impedance while keeping manufacturing costs low.
Confirming specifications with the manufacturer is an important process. Since the combinations of dielectric thickness and copper thickness supported by each manufacturer are limited, it is advantageous for both manufacturing cost and lead time to check the manufacturer's standard specifications at the early design stage and determine the stackup based on them.
Utilizing impedance calculation tools involves back-calculating the trace width required to achieve the target characteristic impedance (100Ω for differential signals, 50Ω for single-ended, etc.) using the determined stackup (dielectric thickness, dielectric constant, and copper thickness). Saturn PCB Toolkit and KiCad's built-in calculation functions fall into this category and will be covered in detail in FC39.
4-Layer PCB Design Checklist
We will organize the items that should be checked upon completion of the stackup design.
For layer configuration verification, check whether there is a continuous GND plane or an appropriately decoupled power plane directly below the signal layer, whether power plane splitting is kept to a minimum, and whether the stackup is symmetrical (to prevent warping).
For layer transition verification, check whether GND stitching vias are placed at layer transition points for high-speed signals or differential pairs, and whether there is sufficient decoupling where signals cross different voltage boundaries on the power plane.
For manufacturability verification, check whether the selected stackup conforms to the PCB manufacturer's standard specifications and whether the combination of dielectric thickness and copper thickness can achieve the target impedance.
Summary
A 4-layer PCB follows the basic pattern of "Signal-GND-Power-Signal" or "Signal-GND-GND-Signal," physically realizing the principles of GND plane continuity and return current paths explained in FC24 and FC25. While splitting the power plane is electrically necessary, if a signal crosses that boundary, a return current path must be ensured through dense decoupling. Selecting a stackup is a process of choosing a combination of dielectric thickness and copper thickness that can achieve the target characteristic impedance while ensuring consistency with the PCB manufacturer's standard specifications. In the next installment, FC32, we will explain via design—via technologies for high-speed signals such as stubs, back-drilling, and via-in-pad.