In the previous article, we explained the framework of thermal design. In this article, FC30, we will address the limitations of DRC (Design Rule Check). As a conclusion to the Hardware Design series, we will organize why the principles of power design, ground design, return current, EMI countermeasures, and thermal design explained so far cannot be guaranteed by automated check tools alone, and clarify the areas where human review is essential.
What DRC can detect
First, let's organize the items that DRC (and ERC: Electrical Rule Check) can reliably detect.
Geometric design rule violations are the area where DRC excels. Geometric constraints related to manufacturability (DFM), such as minimum trace width, trace spacing, minimum via diameter and annular ring, clearance between copper foil and board edges, and overlap between silkscreen and copper foil, are reliably detected by DRC.
Logical errors in electrical connections are handled by ERC. These include unconnected pins, pins not connected to power, and discrepancies between the schematic and PCB layout (netlist mismatches).
In addition to these items, KiCad's DRC can also detect differential pair length matching (tolerance settings), minimum annular rings, and copper slivers (excessively thin fragments of copper foil). The latest version also includes more advanced checks (proximity of multiple nets, placement constraints between specific components).
While these checks guarantee the "grammatical correctness" of the design, much of the "semantic correctness" (EMI, heat, signal quality) explained in this series is outside the scope of DRC.
Mistake 1 that DRC cannot detect: Unintended GND plane splitting
The issue of GND plane splitting, explained in detail in FC24, is a typical example that cannot be detected by DRC.
From a DRC perspective, even if there is a cut in the GND plane, it is not judged as an "error" as long as it does not cause an electrical short or disconnection. Even if a part of the GND plane is thinly divided by other traces, if the planes on both sides are electrically connected via another path (a detour route), it is "normal" in terms of DRC.
However, as explained in FC25, this state of being "electrically connected but physically detoured" causes critical return current path problems for high-frequency signals. DRC only checks for DC-level connectivity and does not have the capability to evaluate effective impedance or the length of detour paths at high frequencies.
Detection methods are limited to visual confirmation in the 3D view (a method repeatedly recommended in the previous series) or analysis using electromagnetic field simulation tools. Some EDA tools (such as Altium Designer's PDN Analyzer) have dedicated features to visualize this type of problem, but they are not included in KiCad's standard DRC.
Mistake 2 that DRC cannot detect: Switching loop area
The DC-DC switching loop area, which was repeatedly emphasized in FC26–FC27, cannot be directly evaluated by DRC either.
While DRC has the capability to calculate trace lengths and areas between components, it lacks the ability to evaluate the physical consequence of "the strength of EMI radiated by this loop." Although you can set a "maximum trace length" as a design rule, the designer must individually judge whether that corresponds to an appropriate loop area.
Evaluation of the switching loop is primarily done through visual review of the layout (checking whether the input capacitor, MOSFET, inductor, and output capacitor are placed in the intended shortest path). Some SI (Signal Integrity) analysis tools have loop inductance calculation features, but they are often not integrated into general FC development workflows.
Mistake 3 that DRC cannot detect: Effectiveness of decoupling capacitors
The relationship between the placement distance of decoupling capacitors and ESL, explained in FC23, is also a blind spot for DRC.
DRC can confirm whether a capacitor "exists" or is "connected to the correct net," but it does not evaluate the physical effectiveness, such as "how many millimeters the trace length from the IC pin is, and how much the SRF decreases as a result."
Even if it is the same "0.1µF decoupling capacitor" on the schematic, the effective performance differs significantly between a placement 1mm from the IC pin and one 10mm away. This difference cannot be distinguished by DRC's netlist consistency check.
The basic detection method is a layout review (checking the actual distance from each decoupling capacitor to the IC pin visually or using the tool's distance measurement function). While some advanced EDA tools have a feature that allows setting a rule to check if a decoupling capacitor exists within a specified distance from an IC pin, the reality is that standard FC development often relies on manual review.
Mistake 4 that cannot be detected by DRC: Layer change issues for return current
The lack of GND stitching vias when signals cross layers, which was explained in FC25, is also a problem that is difficult for DRC to capture.
While DRC can check the geometric correctness of vias (diameter, drill size, annular ring), design decisions such as "is a GND stitching via for return current needed near this signal via?" are not usually included in DRC rule sets.
Although this can be defined as a particularly complex rule (e.g., "require a GND net via within 2mm of a specific signal net via"), few FC development teams actually set up and operate with custom rules at this level. In many cases, they rely on manual checks based on the designer's knowledge and experience.
Mistake 5 that cannot be detected by DRC: Validity of thermal design
The thermal design explained in FC29 is also outside the scope of DRC.
While DRC can confirm the geometric correctness of copper foil area and via placement, general DRC tools do not have thermodynamic evaluation functions to determine if a specific copper foil area can dissipate a certain amount of heat.
Collaboration with dedicated thermal analysis tools (such as Ansys Icepak, introduced previously) is necessary, but this is treated as a separate workflow from the standard PCB design flow and is often omitted in many small-scale FC developments.
Why human review is necessary: Understanding design intent
The essence common to these DRC blind spots is that while DRC checks for "compliance with rules," the problems raised in this article require evaluating the "physical validity of design intent."
DRC can only compare against predefined rules (trace width, clearance, etc.). On the other hand, judgments such as "is this switching loop an appropriate size?", "is this GND split really necessary?", or "is this decoupling capacitor close enough?" can only be evaluated by a human who understands the operating principles of the circuit (the physics explained throughout this series).
This is the reason why I have emphasized "physical understanding" throughout the FC series. Passing DRC is a necessary condition, but it is not a sufficient condition.
Building a systematic review process
I will organize a practical review process to compensate for the limitations of DRC.
A checklist-based review is a process of integrating the various checklists presented throughout this series (EMI articles, ESC articles, Hardware Design series) and systematically confirming them upon design completion. The implementation checklists shown in FC11 (GNSS) and FC27 (EMI countermeasures) form the foundation for this.
Peer review by multiple people is an effective method for discovering problems from a different perspective that the designer themselves might overlook. Problems of the "it works but is not optimal" type, such as EMI or thermal design, are particularly prone to being overlooked due to the designer's own bias (the psychological tendency to justify one's own design), making third-party review effective.
3D view and layer-by-layer visualization review is a process of displaying GND plane continuity, component placement, and routing paths layer by layer in tools like KiCad to visually discover problem areas. In particular, unintended splitting of GND planes is most reliably detected by visual confirmation when viewing layers individually.
Creating a database of past problems is a continuous improvement process of recording EMI, thermal, and signal quality issues discovered during prototyping and actual machine testing, and reflecting them in review items for the next design. The "feedback from actual measurements with near-field probes" mentioned in FC27 becomes the information source for building this database.
Expanding areas that can be automated
Rather than relying entirely on manual labor, it is also valuable to make efforts to expand the scope of DRC.
Creating custom DRC rules involves using the custom rule features provided by KiCad or Altium Designer to define unique rules, such as the aforementioned 'GND stitching via requirement near signal vias.' This allows you to incorporate recurring problem patterns specific to a project into automated detection.
Script-based verification involves using PCB design data (such as KiCad's Python scripting API) to create your own scripts, for example, to automatically calculate the distance between decoupling capacitors and IC pins. You can partially automate physical effectiveness evaluations that are not covered by standard DRC using custom scripts.
Incorporating simulation tools means integrating the thermal simulations or SI (Signal Integrity)/PI (Power Integrity) analysis tools introduced previously as standard steps in the PCB design flow. This allows some problems that 'cannot be detected by DRC' to be covered by other automation tools.
While these automation extensions do not completely replace human review, they have the effect of reducing the burden of review and lowering the risk of oversight.
Practical Design Review Checklist (Integrated Version)
We will organize a final checklist that integrates the content of the entire Hardware Design series (FC21–FC30).
For power system verification, check whether the hierarchical structure of the power tree is appropriate (FC21), whether LDOs/DC-DC converters are used appropriately for each voltage rail (FC22), and whether decoupling capacitors are placed within 1mm of each IC pin (FC23).
For ground return current verification, check whether there are unnecessary splits in the GND plane (FC24), and whether the GND plane is continuous directly under signal traces and if GND stitching vias are placed at layer transition points (FC25).
For EMI countermeasure verification, check whether the DC-DC switching loop is minimized and whether the wiring length of high-speed signals is minimized (FC26–FC27).
For EMC and thermal design verification, check whether ESD/surge protection is applied to external interfaces (FC28), and whether heat-generating components and sensors are physically separated and heat dissipation paths are designed appropriately (FC29).
This checklist is intended to be used in the human review phase after running DRC.
Summary
While DRC reliably checks geometric design rules and electrical connectivity, it cannot detect problems involving 'physical meaning' such as unintended splits in the GND plane, switching loop area, effective placement distance of decoupling capacitors, layer transition issues for return currents, or the validity of thermal design. These are areas where human review based on a physical understanding of circuit operation, as explained in FC21–FC29, is essential. By combining a systematized checklist, multi-person reviews, visual confirmation via 3D views, and partial automation extensions through custom DRC rules and scripts, you can practically compensate for the limitations of DRC. This concludes the Hardware Design series. Starting with the next installment, FC31, we will begin the PCB Design series, where we will explain professional PCB design techniques for handling higher-speed signals, such as 4-layer board design, via design, differential pairs, and transmission line theory.