In the previous article, we explained the importance of a continuous GND plane as a principle of ground design. In this article, which is FC25, we will cover return current. We will delve into the physical law mentioned last time—that 'return current follows the path of least resistance'—from its fundamental principles to practical layout design.
What is return current?
All current forms a loop. If there is current flowing from the signal source to the IC (forward current), an equal amount of current must return to the signal source through the GND (return current). This entire round-trip loop is the 'circuit'.
In circuit diagrams, only the forward path (signal line) is drawn, and the return path is simply omitted with a 'GND' symbol. However, on an actual PCB, the path this return current takes is a critical physical phenomenon that determines both signal quality and EMI.
The misconception that 'signals can pass anywhere on the GND' is the primary cause of EMI problems. Return current follows specific paths according to physical laws, and problems arise when those paths differ from the designer's intent.
Why return current chooses the shortest path—the law of inductance minimization
There is a physical law that determines which path return current takes based on frequency.
At low frequencies (near DC), return current chooses the path of least resistance. This is a simple consequence of Ohm's Law; if there are multiple parallel paths, current concentrates in the path with the lowest resistance (the widest and shortest path).
At high frequencies, return current chooses the path of least inductance. This is a crucial physical phenomenon that is counterintuitive.
Let's verify why inductance becomes dominant using an equation. The impedance of a circuit is:
Z = R + jωL
As ω increases (frequency rises), the ωL term overwhelmingly exceeds R. For signals above 100 kHz, the inductance term becomes dominant in almost all practical wiring.
As a result, high-frequency current does not choose the 'path of least resistance' but rather the 'path of least inductance,' which is the path that minimizes the loop area.
The relationship between loop area and inductance
The inductance of a loop is approximately proportional to the area enclosed by that loop.
As a simplified formula, the inductance of a rectangular loop is:
L ≈ (μ0/π) × length × ln(2×height/width)
The 'height' is the distance between the forward path and the return path (i.e., the height of the loop). The smaller the height (the closer the signal line and return path are), the smaller the inductance becomes.
This is the physical basis for the phenomenon where 'if there is a GND plane directly under the signal wiring, the return current flows directly beneath it.' The distance between the signal wiring and the GND plane (the interlayer distance of the board, typically 0.1 to 0.3 mm) becomes the 'height' between the forward and return paths. Since this is orders of magnitude smaller than a case where the wiring passes several centimeters away, the path directly under the signal has overwhelmingly lower inductance.
The effect of GND plane slits on return current
I will explain specifically how the GND plane splits and gaps discussed in the previous ground design section cause problems from the perspective of return current.
If there is a slit (gap) in the GND plane directly beneath a signal trace, the return current cannot jump across that slit. Because current must flow through a physically existing conductor, it is forced to take a path that bypasses the slit.
In many cases, the bypass path significantly increases the loop area. The current must take a large detour to the nearest conductor (another trace, via, or connected part of the plane) that bridges the two sides of the slit, which is the direct mechanism for the "EMI degradation due to increased loop area" explained in the EMI series.
As a concrete scenario, consider a 4-layer board where there is a slit in inner layer 2 (GND) and a trace on inner layer 1 (signal layer) crosses that slit. The high-frequency signal current stops at the slit, searches for the nearest via (a via connecting planes or a GND on another layer), takes a large detour, and then rejoins the path on the other side of the slit. This detour loop functions as a powerful radiating antenna.
This is the physical explanation for why the design of "splitting analog GND and digital GND and having signal traces cross the boundary" discussed in FC24 causes problems. While it is possible for a trace to cross a boundary (slit), it becomes an impassable wall for the return current of that signal.
Return current via power planes
I will explain the behavior of return current when the layer directly beneath the signal layer is a power plane (not GND).
At high frequencies, a power plane and a GND plane can be considered to be at almost the same potential (in terms of AC/high-frequency) if there are appropriate decoupling capacitors. This is because the decoupling capacitors discussed previously provide a low-impedance coupling between the power plane and the GND plane.
For this reason, even if the layer directly beneath the signal layer is a power plane, the return current can return through that power plane if there is sufficient decoupling. However, this is limited to cases where decoupling capacitors are placed with sufficient density near the signal path.
If the decoupling between the power plane and the GND plane is insufficient, the return current cannot pass through the power plane and will detour to a more distant GND plane. In multilayer board stack-up design (detailed from FC31 onwards), it is necessary to make a design decision to intentionally use a GND plane for the layer adjacent to the signal layer, or to ensure dense decoupling if a power plane is used.
Signals crossing layers—vias and return current
When a signal crosses layers (passes through a via) in a multilayer board, the return current must also change layers accordingly.
If a signal moves from layer 2 (directly under GND) to layer 4 (directly under another GND) via a via, the signal's return current must also move from the GND on layer 2 to the GND on layer 4.
If the GND planes on layer 2 and layer 4 are not directly connected (e.g., there is another signal layer in between), the return current will take a large detour to find a connection point.
The countermeasure is the placement of a return current via (Stitching Via). By placing a dedicated via that connects the GND planes to each other right next to the signal via, you provide a short path for the return current. For layer changes of high-speed differential signals (USB, CAN), it is a standard design rule to place a GND stitching via in the immediate vicinity (within 1–2 mm) of the signal via.
In the case of a differential pair, when the two signal lines forming the pair cross layers, place at least one GND stitching via near both signal vias, and ideally on both sides. This design is important for maintaining the high-frequency characteristics of differential signals (such as CAN) explained in the NAV/ESC series.
Return current problems when changing power layers
A specific problem arises when a signal changes layers while crossing planes of different power voltages.
For example, if a signal moves from layer 2 (directly under a GND plane) to layer 4 (directly under a 3.3V power plane), the return current must move between the GND plane and the 3.3V plane. If these two planes are not directly connected (naturally, they cannot be directly connected as they are power and GND), the return current moves via the capacitive coupling (decoupling capacitor) between them.
In this scenario, by placing multiple decoupling capacitors (between GND and 3.3V) near the signal via, you provide a low-impedance path for the return current to move. Ideally, these decoupling capacitors should be placed within a few millimeters of the signal via.
This type of return current issue becomes particularly severe with high-speed digital signals (several hundred MHz or higher) and is a point that designers often overlook. For the layout of high-speed peripherals on the STM32 (SDMMC, USB HS, etc.), it is recommended to plan the stack-up and floorplan in advance to ensure that signals do not cross different power planes.
Measuring and Evaluating Loop Area
We will organize the methods for evaluating the loop area of a designed layout.
Visual confirmation in a 3D view involves using PCB design tools (such as the KiCad 3D viewer) to visually verify the continuity of signal traces and the GND plane directly beneath them. Focus on checking slits and layer transition points.
Current loop simulation uses more advanced tools (Ansys SIwave, Altium PDN Analyzer, etc.) to visualize actual current distribution and loop area through electromagnetic field simulation. While the introduction cost may not be justified for small-scale boards like FC designs, it is a worthwhile investment for industrial and high-reliability FC development.
Actual measurement using near-field probes, as explained in the EMI series, is the final verification method to confirm whether loop area issues are actually manifesting as EMI. It is important to have a feedback loop based on measurements from the actual hardware, not just theoretical design.
Layout Strategy Based on Return Current Principles
Based on the discussions so far, we will organize practical layout strategies.
Prioritize having a GND plane directly beneath signal layers at all times. If using a power plane, ensure sufficient decoupling near the signal path.
Minimize layer changes (vias), and when they are necessary, always include GND stitching vias. Strictly adhere to this principle, especially for high-frequency signals (clocks, high-speed communication).
Avoid cuts in the GND plane as much as possible, and if splitting is unavoidable (as in the special cases explained in FC24), design the floorplan so that signal traces do not cross those cuts.
A hierarchical floorplan is effective, where power sequences and floorplans are linked, placing ICs that handle high-frequency signals in areas where the GND plane is most continuous, and placing low-speed, low-noise-sensitive signals in the peripheral areas.
These principles will be developed into more concrete implementations in the PCB design series from FC31 onwards (4-layer board design, differential pairs, transmission lines).
Practical Example—Return Current Design for Sensor Buses
Using the IMU's SPI bus as an example, we will demonstrate a practical design that considers return current.
The IMU (see FC6–FC8) is connected to the MCU via SPI. Four signal lines—SCK, MOSI, MISO, and CS—flow from the MCU to the IMU or bidirectionally. The primary design decision is to ensure a continuous GND plane directly beneath these signals.
If the wiring between the IMU's CS pin and the MCU's GPIO pin passes through inner layers (when surface wiring is congested), always place GND stitching vias near the layer-change vias.
Since the SPI clock (SCK) is the highest frequency signal (several tens of MHz), prioritize securing its return current path. When designing the layout around the IMU, consider this constraint first to ensure the SCK trace does not cross any slits in the GND plane.
The guideline of "keeping IMU SPI wiring short," explained in the previous IMU implementation series (FC6), has the effect of not only shortening the trace length itself but also minimizing the return current loop area.
Summary
At high frequencies, return current always chooses the path that minimizes loop inductance, which is directly beneath the signal trace. Slits in the GND plane or improper layer changes force this return current to detour, increasing the loop area and becoming a direct cause of the radiated noise explained in the EMI series. When using a power plane directly beneath a signal, sufficient decoupling is essential, and when changing layers, the placement of GND stitching vias is mandatory. Understanding this physical law is the basis for the ground design principles in FC24 and serves as the foundation for all discussions in the subsequent PCB Design series. In the next installment, FC26, we will reorganize the EMI sources—the generation mechanisms of radiated and conducted noise in FC design—at the circuit level.