In the previous article, we explained the differences between LDOs and DC-DC converters. In this article, which is FC23, we will cover decoupling capacitors. We will explain in detail the physics, placement, and capacitance selection of decoupling capacitors, which are the most fundamental yet highly effective components for power supply noise suppression.
The Role of Decoupling Capacitors
Decoupling capacitors are placed near the power pins of an IC and function as local charge reservoirs that meet instantaneous current demands.
When an IC operates, it requires large, instantaneous currents due to the switching of internal circuits (MCU clock operations, digital output switching). If one attempts to supply this current from the power supply wiring (the path from the DC-DC or LDO located several centimeters to tens of centimeters away from the VBAT) every time, a voltage drop (V=L×dI/dt) occurs due to wiring inductance, causing the power supply voltage on the IC side to drop momentarily.
By placing a decoupling capacitor very close to the IC, it locally meets these instantaneous current demands, eliminating the need to go through the power supply wiring. Because the wiring is short, parasitic inductance is low, enabling high-speed current supply.
The same principle explained in the EMI series, 'minimizing the switching loop,' applies here as well. The role of a decoupling capacitor is to physically minimize the current loop of the IC.
Difference Between Ideal and Real Capacitors
To understand decoupling capacitor design, it is essential to understand that real capacitors have characteristics that differ from ideal capacitors.
The equivalent circuit of a real capacitor is represented by an ESR (Equivalent Series Resistance), an ESL (Equivalent Series Inductance), and an ideal capacitance C connected in series.
The frequency characteristics of impedance are:
Z(f) = ESR + j(2πfL_ESL - 1/(2πfC))
In the low-frequency region, capacitive reactance 1/(2πfC) is dominant, and impedance decreases as the frequency increases.
In the high-frequency region, inductive reactance 2πfL_ESL due to ESL becomes dominant, and impedance increases as the frequency increases.
The Self-Resonant Frequency (SRF) is the frequency at which capacitive reactance and inductive reactance are equal:
f_SRF = 1/(2π√(L_ESL×C))
At this SRF, the impedance reaches its minimum value (ESR only), and the capacitor attenuates noise most effectively. At frequencies higher than the SRF, the capacitor behaves more like an inductor, and the noise attenuation effect is lost.
Relationship Between Capacitance and SRF
The larger the capacitance, the lower the SRF. This is the reason for placing multiple capacitance values in parallel in decoupling design.
Here is a summary of typical SRF guidelines for MLCCs.
10µF (0805 package, ESL approx. 1nH): SRF ≈ 1/(2π√(1nH×10µF)) ≈ 1.6MHz
1µF (0603 package, ESL approx. 0.5nH): SRF ≈ 1/(2π√(0.5nH×1µF)) ≈ 7.1MHz
0.1µF (0402 package, ESL approx. 0.3nH): SRF ≈ 1/(2π√(0.3nH×0.1µF)) ≈ 29MHz
0.01µF (0201 package, ESL approx. 0.2nH): SRF ≈ 1/(2π√(0.2nH×0.01µF)) ≈ 113MHz
From the SRF, it can be understood that large-capacitance capacitors are effective against low-frequency noise (several hundred kHz to several MHz), while small-capacitance capacitors are effective against high-frequency noise (several tens of MHz or higher).
Parallel Placement of Multiple Capacitances: Designing Impedance Curves
Since a single capacitance value has a limited frequency coverage range, it is standard practice to place multiple capacitors in parallel to keep the impedance low over a wide bandwidth.
A typical configuration is a combination of 10µF + 1µF + 0.1µF + 0.01µF. Because each capacitance has a different SRF, they attenuate noise in their respective optimal frequency bands.
The combined impedance when connected in parallel is not a simple parallel sum; complex resonance and anti-resonance occur near the SRF of each capacitor. When capacitors with different values are connected in parallel, an anti-resonance frequency occurs between each SRF, and at that frequency, the combined impedance may be worse than that of the individual capacitors.
Setting an appropriate capacitance ratio is effective for suppressing anti-resonance. As a rule of thumb, maintaining a ratio of about 10 times between adjacent capacitance values (a decade configuration such as 10µF:1µF:0.1µF) can suppress anti-resonance peaks.
In actual design, it is recommended to use SPICE simulation or impedance curve tools provided by capacitor manufacturers (such as Murata SimSurfing) to verify the impedance characteristics of the actual layout.
Relationship Between Placement Distance and ESL
The effectiveness of a decoupling capacitor depends not only on the capacitance selection but also significantly on the placement distance (trace length).
Inductance due to traces is approximately 1nH per 1mm. If a capacitor is placed 5mm away from an IC pin, approximately 5nH of inductance is added by the trace, which significantly exceeds the ESL of the capacitor itself (about 0.3 to 1nH).
The reduction in effective SRF is caused by this additional inductance. Even if a 0.1µF capacitor (ESL=0.3nH) has an SRF ≈ 29MHz on its own, if it becomes 5.3nH (0.3+5) due to a 5mm trace:
f_SRF_actual = 1/(2π√(5.3nH×0.1µF)) ≈ 6.9MHz
The SRF drops significantly from 29MHz to 6.9MHz, and the effectiveness against the high-frequency noise it was originally intended to cover is lost.
The priority for placement is that capacitors with higher SRF (smaller capacitance) must be placed closer to the IC pins. A standard pattern is to place the 0.01µF closest to the IC, followed by the 0.1µF, with the 1µF and 10µF placed slightly further away.
The effect of vias is also added to the placement distance. When using vias to connect surface-mount capacitors to an internal GND plane, the vias themselves add about 0.5 to 1nH of inductance. A technique of placing multiple small-diameter vias (via stitching) directly under the capacitor pads to distribute and reduce inductance is used in high-speed digital circuits.
Decoupling Design for Each Power Pin
Organize the correspondence between the IC power pin layout and the decoupling capacitors.
For ICs with multiple power pins (the STM32H7 has many VDD/VSS pairs), the principle is to place an individual decoupling capacitor for each power pin pair. Attempting to decouple multiple pins with a single capacitor increases wiring distance, which raises ESL and reduces effectiveness.
The STM32H7 datasheet specifies the recommended decoupling capacitance. A common recommendation is to place 0.1µF at each VDD pin and distribute several 1µF to 4.7µF bulk capacitors across the VDD supply.
Decoupling for VCORE (core power) is more stringent. The STM32H7's internal SMPS converter requires capacitors within specific capacitance and ESR ranges (refer to the Power Supply Scheme in the datasheet); failing to follow this may cause the SMPS to operate unstably.
Role of Bulk Capacitors
Apart from decoupling capacitors, there is a design practice of placing large-capacity bulk capacitors (10–100µF) across the power system.
The role of bulk capacitors is to absorb voltage fluctuations at low frequencies (several hundred kHz or less). They mitigate voltage drops immediately after the DC-DC converter output or during moments when multiple ICs demand high current simultaneously.
Electrolytic capacitors (tantalum, aluminum electrolytic, polymer) are often used as bulk capacitors; while they are easier to make high-capacity than MLCCs, they have higher ESR. The principles for selecting low-ESR types explained in the previous series on ESC circuit design (input capacitors) apply here as well.
The division of roles between bulk capacitors and decoupling capacitors can be organized by frequency band. It is a hierarchical structure where bulk capacitors (10–100µF) handle low-frequency, high-current fluctuations; medium-capacity MLCCs (1–10µF) handle the intermediate frequency band; and small-capacity MLCCs (0.01–0.1µF) handle high-frequency, steep edges.
PCB Layout Patterns for Decoupling Capacitors
The following summarizes recommended patterns for actual PCB layout.
The shortest connection to the IC pad is the top priority. Wiring from the capacitor pad to the IC power pin should be as thick and short as possible. Ideally, place the capacitor right next to the surface-mount component and keep the wiring length under 1mm.
Handling cases where power pins and GND pins are not adjacent is also important. In many IC packages where VDD and VSS are far apart, minimize effective inductance by carefully placing capacitors and vias. A standard design is to use the shortest path to place vias on both the VDD and VSS sides and connect them via internal planes.
Connection to the GND plane should be consistent with the GND plane continuity principles explained in the EMI series. The GND side of the decoupling capacitor should be connected directly to the GND plane using dedicated vias, avoiding routing GND on the surface layer.
For multi-layer boards, it is common to place capacitors on the component side (top layer) and connect them to internal power/GND planes through vias on or near the back of the IC. For BGA package ICs, 'bottom-side decoupling,' where capacitors are placed on the back of the board under the BGA package, is also used in high-speed digital circuits.
Decoupling Design for Sensor Circuits
The following summarizes the specificities of decoupling design for sensor ICs such as IMUs and GNSS.
Decoupling for sensors requires smaller capacity and higher quality design than for MCUs. For high-sensitivity sensors like IMUs (see FC6–FC8), the standard configuration is to place a 0.1µF MLCC as close as possible (within 1mm) to the sensor IC, adding a 1µF bulk capacitor if necessary.
Low-ESR and high-stability MLCC types (C0G/NP0 dielectric) are recommended for sensors. X7R and Y5V dielectrics have large capacitance fluctuations due to temperature and voltage, making them unsuitable for precise analog circuits. While C0G/NP0 has extremely small capacitance fluctuations, it has the constraint that high-capacity versions are physically large. Generally, a split is used where X7R is used for the main decoupling capacity (0.1µF or more) and C0G/NP0 is used for the final stage small capacity (several nF to several tens of nF).
Output decoupling for GNSS LDOs is important to maximize the performance of the high-PSRR LDOs explained previously. Placing excessive capacity at the LDO output can interfere with the LDO's phase compensation design and create a risk of oscillation. It is essential to strictly adhere to the recommended output capacity range (including the ESR range) stated in the datasheet.
Verification Methods for Decoupling
This article explains how to verify the effectiveness of a designed decoupling circuit through actual measurements.
Power supply impedance measurement is performed using a network analyzer or impedance analyzer, measuring the impedance seen from the power pins via frequency sweeping. A target impedance is set, and it is confirmed that the impedance remains below this value across the entire frequency band.
The target impedance is calculated from the allowable ripple voltage ΔV and the maximum transient current ΔI as follows:
Z_target = ΔV / ΔI
For example, in the case of a 3.3V power supply with an allowable ripple of ±50mV (1.5%) and a transient current of 500mA:
Z_target = 0.05V / 0.5A = 0.1Ω
The type, capacitance, and placement of decoupling capacitors are designed to keep the impedance below this 0.1Ω across the entire frequency band (DC to several hundred MHz).
Direct measurement with an oscilloscope is a simpler verification method. By placing a probe near the power pin (with the shortest possible GND lead), the power supply ripple during IC operation is observed directly. By comparing the ripple amplitude before and after adding decoupling, the effectiveness of design changes can be evaluated quantitatively.
Summary
Decoupling capacitors should be designed by understanding the physical characteristics of real capacitors, specifically ESL and SRF, and by combining parallel placement of multiple capacitances (e.g., 10µF + 1µF + 0.1µF + 0.01µF) with the shortest possible wiring distance (ideally within 1mm). Because the increase in inductance due to wiring length significantly lowers the SRF, close placement to the IC pins is just as important as capacitance selection. For sensor circuits, selecting low-ESR, high-stability MLCCs and adhering to the LDO's recommended capacitance range are particularly critical. In the next issue, FC24, we will explain ground design—the design principles of GND plane splitting, star connections, and single-point grounding.