In the previous article, we explained the power architecture of the entire FC. In this article, FC22, we will cover LDOs (Low Dropout Regulators) and DC-DC converters (switching regulators). We will explain in detail everything from the differences in their operating principles to the criteria for deciding which one to choose for FC design.
Operating Principle of LDO
An LDO is a type of linear regulator that controls voltage by dissipating the difference between the input voltage and the output voltage as heat using a variable resistor (pass transistor).
The basic configuration consists of a pass transistor (usually PMOS or PNP), a reference voltage source (bandgap reference), an error amplifier, and a feedback resistor divider. The output voltage is monitored via feedback, and the difference from the reference voltage is amplified by the error amplifier to control the gate (or base) of the pass transistor.
The calculation for power loss is simple:
P_loss = (Vin - Vout) × Iout
In the case of VBAT=5V, Vout=3.3V, and Iout=200mA:
P_loss = (5-3.3) × 0.2 = 0.34W
The larger the voltage difference and the higher the current, the greater the loss. This is why LDOs are unsuitable for 'large voltage differences and high currents'.
The dropout voltage is the minimum input-output voltage difference required for an LDO to operate correctly. Low dropout models (LDO = Low Dropout) can reduce the voltage difference to about 100–300mV, allowing them to operate even when the input voltage is close to the output voltage.
Operating Principle of DC-DC Converters
A DC-DC converter (switching regulator) uses an inductor and switching elements to perform voltage conversion by magnetically storing and releasing energy.
The basic operation of a buck converter involves repeating a cycle where current flows through an inductor to store energy while the switch is on, and that energy is released to the output while the switch is off. The output voltage is determined by the duty ratio D:
Vout = D × Vin
Ideally, power loss is theoretically low, and conversion efficiency reaches 85–95%. Unlike an LDO, it does not generate losses dependent on the voltage difference, so it maintains high efficiency even with large voltage conversion ratios (e.g., VBAT 25V to 5V).
The principles of MOSFET switching, gate drivers, and dead time explained in detail in ESC11–ESC18 also apply to DC-DC buck converter ICs. For small DC-DC converters used in FC, integrated solutions that combine these circuits into a single chip are the mainstream.
Efficiency Comparison: Concrete Numerical Calculation
We will compare the efficiency of an LDO and a DC-DC converter using a concrete example.
Case 1: VBAT (5S, 18.5V) → 3.3V, 300mA
When using an LDO:
P_loss = (18.5-3.3) × 0.3 = 4.56W
Efficiency = (3.3×0.3)/(18.5×0.3) = 17.8%
When using DC-DC (assuming 90% efficiency):
P_loss = (3.3×0.3)/0.9 - (3.3×0.3) = 0.11W
Efficiency = 90%
In this extreme case, the LDO generates as much as 4.56W of heat, making heat dissipation on the FC board a serious issue. With a DC-DC converter, it only requires 0.11W.
Case 2: 5V to 3.3V, 100mA (LDO for sensors)
When using LDO:
P_loss = (5-3.3) × 0.1 = 0.17W
Efficiency = 66%
When using DC-DC (assuming 85% efficiency, efficiency drops slightly at low currents):
P_loss = (3.3×0.1)/0.85 - (3.3×0.1) = 0.058W
Efficiency = 85%
In this case with a relatively small voltage difference and current, the LDO's loss of 0.17W is within a realistic range, and no major heat dissipation issues arise.
Comparison of Noise Characteristics: Why LDOs are Chosen
While DC-DC is always superior in terms of power efficiency, the reason LDOs are frequently used for sensors in FC design is their noise characteristics.
Because LDOs operate linearly, there is fundamentally no switching noise in their output. Output ripple is determined by input voltage ripple and PSRR (Power Supply Rejection Ratio), and high-quality LDOs have excellent PSRR even at high frequencies (around 40–60 dB at 100 kHz).
For DC-DC, output noise appears as ripple at the switching frequency (several hundred kHz to several MHz) and its harmonics. While this can be reduced with an LC filter, it cannot be completely eliminated.
For high-sensitivity sensors like IMUs and GNSS, DC-DC switching noise leads directly to a degradation of the noise floor. As explained in the EMI article from two series ago, GNSS CN0 and IMU bias stability are sensitive to this noise.
For this reason, a typical pattern in FC design is a two-stage configuration: 'efficiently step down high current with a DC-DC converter, then clean up the output with an LDO.' A configuration of VBAT → DC-DC → 5V → LDO → 3.3V (for sensors) is a design that satisfies both efficiency and noise requirements.
Details on PSRR (Power Supply Rejection Ratio)
PSRR of an LDO is a key indicator that determines the quality of the sensor power supply.
PSRR is an indicator showing how much input voltage fluctuation is transmitted to the output, expressed in dB:
PSRR(dB) = 20 × log10(ΔVin / ΔVout)
A PSRR of 60 dB means that 1/1000th of the input ripple appears at the output.
PSRR is frequency-dependent. At low frequencies (DC to several kHz), the feedback of the error amplifier is effective, resulting in high PSRR (60–80 dB), but at high frequencies (several hundred kHz or higher), the response of the error amplifier cannot keep up, causing PSRR to drop (to around 20–30 dB).
The switching frequency of DC-DC converters (several hundred kHz to several MHz) often overlaps with the band where LDO PSRR drops, which is why switching noise cannot be sufficiently removed even if the DC-DC output is stepped down directly by an LDO. A design that adds an LC filter before the LDO to attenuate switching frequency components in advance is effective.
High-PSRR LDO models (such as the TPS7A47 and LT3045) are high-performance products that maintain a PSRR of 40 dB or more even at 1 MHz, and they are used in designs specialized for GNSS/IMU power supplies. Although they are more expensive than general-purpose LDOs, they are worth the investment for noise-sensitive sensors.
Selection criteria for DC-DC converters
We will organize the specifications that should be checked when selecting a DC-DC converter.
The input voltage range must cover the maximum battery voltage (at full charge). For a 6S LiPo, the maximum is 25.2V, so we select a model with an absolute maximum rating of 30V or higher, considering a margin.
Switching frequency is a trade-off between EMI and size. 500kHz to 2MHz is the typical range; higher frequencies allow for smaller inductors, but as explained in the EMI series, radiated noise increases.
The output current rating should have a margin of 1.5 to 2 times the actual load.
The choice between an integrated (module) type or a discrete component configuration is also important. Integrated types (such as the TPS62xx series, where everything except the inductor is integrated into one package) are easy to design and have fewer components, but offer less flexibility. Discrete configurations (controller IC + external MOSFET + inductor) offer high freedom for high-current, high-efficiency designs, but increase design difficulty.
In FC design, it is common to use integrated DC-DC converters for generating the main power supply for medium currents (1-3A), and discrete component configurations for special applications requiring high current (such as servo power for large aircraft).
Selection criteria for LDOs
We will organize the selection criteria for LDOs.
Dropout voltage is important in applications where the difference between input and output voltage is small. For a 1.7V difference, such as 5V to 3.3V, a standard LDO is sufficient, but a margin considering input voltage fluctuations is necessary.
The output current rating should have a margin for peak current (including inrush current). GNSS modules often have instantaneous current peaks at startup, so check the peak current specification in the datasheet.
As mentioned above, PSRR is the most important metric for sensor LDOs. For general applications (such as MCU I/O), a standard PSRR (around 40dB) is sufficient, but for GNSS/IMU, choose a high-PSRR model.
Noise (output noise voltage) is listed in the LDO datasheet in μVrms units. Low-noise LDOs (10μVrms or less) are suitable for analog circuits and RF circuits (GNSS).
For thermal design, check the required package thermal resistance based on the LDO loss calculation (mentioned above). If the loss is large, choose a package with a power pad (SOT-223, DFN, etc.) and design heat dissipation using PCB copper foil.
Practical usage patterns in FC design
We will organize the selection patterns by power system in actual FC design.
For main power generation (VBAT to 5V, high current), DC-DC is the only choice. Because the voltage difference and current are both large, thermal design would fail with an LDO.
For MCU power (5V to 3.3V, medium current, several hundred mA), an LDO is standard. The susceptibility of the STM32 to digital noise is moderate, and an LDO with moderate PSRR is sufficient. In some high-performance designs, a two-stage DC-DC + LDO configuration is also used to reduce noise.
For sensor power (5V to 3.3V, low current, IMU/GNSS/compass), a high-PSRR LDO is the only choice. As mentioned above, because noise sensitivity is extremely high, quietness is prioritized over efficiency.
For VCORE (STM32 core power, around 1.2V, requiring high current instantaneously), a DC-DC (internal SMPS or external) is common. The STM32H7 supports an internal SMPS step-down converter, allowing for high-efficiency VCORE generation with only an external inductor and capacitor.
When organizing the selection criteria for each power supply system, they can be summarized into three patterns: 'high noise sensitivity and low current → LDO', 'large voltage difference/current and efficiency is important → DC-DC', and 'want both → two-stage DC-DC + LDO'.
Implementation details of the two-stage configuration
Here is the specific implementation of a two-stage DC-DC + LDO configuration.
VBAT (6S, 22.2V) → DC-DC (TPS54331, etc.) → 5V (intermediate voltage) → LDO (TPS7A4700, etc.) → 3.3V (for GNSS)
The ripple of the DC-DC output (5V) is typically around 20 to 50mV. When this is input into an LDO, the ripple at the output (3.3V) is reduced to about 0.2 to 0.5mV due to the LDO's PSRR (about 40dB near 1MHz).
A design that adds a ferrite bead between the DC-DC output and the LDO input is also effective. It increases impedance in the switching frequency band, further suppressing noise intrusion into the LDO. This is the same principle as the method explained in the previous series on EMI countermeasures (filter circuits and PCB layout articles).
The placement and capacitance of the LDO input and output capacitors will be covered in detail in FC23 (Decoupling Capacitors).
System-level evaluation of efficiency and heat generation
We will organize the procedure for evaluating the efficiency of the entire power supply system and reflecting it in the thermal design.
The efficiency of the entire system is calculated by multiplying the efficiency of each stage. In a two-stage configuration of DC-DC (90%) → LDO (66%, 5V → 3.3V, 100mA):
Overall efficiency = 0.9 × 0.66 = 59.4%
Relative to the input power seen from the VBAT side, only 59.4% is ultimately used by the sensor, with the remaining 40.6% lost as heat.
Use the total loss as input for the PCB thermal design (detailed in FC29) to calculate the temperature rise of each heat-generating component (DC-DC IC, LDO).
For long-endurance aircraft where low power consumption is required, the poor efficiency of the LDO directly affects battery consumption. Therefore, it is important to adopt a design philosophy where voltage conversion is completed as much as possible using only DC-DC, and only the final small voltage difference adjustment is performed by the LDO.
Summary
LDOs are inherently low-noise and suitable for sensor power supplies, but they generate losses proportional to voltage difference × current, making them unsuitable for large voltage differences or high currents. DC-DC converters are highly efficient but have switching noise, making them unsuitable for direct power supply to noise-sensitive sensors. The standard pattern for FC design is to use DC-DC for generating the main high-current power supply and a high-PSRR LDO for sensor power. A two-stage configuration (DC-DC → LDO) that combines both is a practical solution that balances efficiency and noise characteristics. In the next installment, FC23, we will explain decoupling capacitors in detail, including placement, capacitance selection, and the effects of ESL.