Last time, we explained the SITL simulation environment. In FC21, the first installment of the Hardware Design series, we will cover power design. The power system of an FC is the foundation that relates to everything from EMI to stability and reliability, and the design decisions made here determine the performance of the entire board.
The scope of performance determined by power design
The power system of an FC is not just about 'creating voltage.' As explained in the EMI series (the series before last), noise in the power system directly degrades sensor accuracy. The quality of the power design affects everything, including the IMU noise floor, GNSS CN0, and compass magnetic noise.
The starting point for FC power design is organizing the requirements: what needs to be supplied with how many volts and how much current. The role of power architecture is to design a system that supplies appropriate voltage, current, and noise levels to the STM32H7 core (see FC3-FC4), IMU (FC6), GNSS (FC11), compass (FC9), barometer (FC10), and various communication interfaces.
Power tree design
In FC design, we design a 'power tree' that hierarchically configures multiple voltage rails.
Input voltage is supplied directly from the battery, and it is common to have multiple input paths such as 3S-12S LiPo (11.1V-44.4V) or 5V USB power. If there are multiple power inputs, a priority circuit (ideal diode ORing) is required.
Main power generation creates the primary intermediate voltage (5V system) from the input voltage. This is the primary step-down stage that handles large currents and serves as the input for multiple LDOs in the subsequent stages.
Sensor system power is stepped down further from the 5V system to 3.3V and supplied to the IMU, GNSS, compass, and barometer. Each uses an independent LDO to prevent mutual noise interference (detailed in FC22).
MCU power is the power system for the STM32 core. The STM32H7 requires multiple voltages, VDD (3.3V, for I/O) and VCORE (1.2V, for the core), which are generated by internal or external regulators.
Peripheral circuit power includes power for sensors, SD cards, and external communication modules, and power design according to the load characteristics of each is required.
Design example of a voltage rail list
We will specifically show the voltage rail configuration of a typical industrial FC (based on STM32H743).
VBAT (input, 3S-6S LiPo, 11.1-25.2V), 5V_MAIN (main power, generated by step-down converter, max 2A), 5V_PERIPH (5V for peripherals, USB power/external sensors), 3.3V_MCU (for MCU, generated by LDO, max 500mA), 3.3V_SENSOR (dedicated for sensors, independent LDO, max 200mA), 1.8V_GNSS (for GNSS module, dedicated LDO), 1.2V_VCORE (STM32 core power, internal SMPS or external LDO).
What is important in this hierarchical configuration is to electrically isolate noise-sensitive sensor systems from noise sources (main power, MCU). The design decision to not take 3.3V_MCU and 3.3V_SENSOR from the same LDO but to use separate systems is the basis of EMI countermeasures.
Primary step-down stage design - SMPS selection
The primary step-down stage that generates 5V_MAIN from VBAT is the part with the highest current and the most heat generation.
The selection criteria for a step-down converter IC are the input voltage range (covering the maximum value of VBAT, 25.2V for 6S full charge or 44.4V equivalent for 12S), output current (total of all loads + margin, usually 2-3A), and switching frequency (trade-off between EMI and size, see the EMI article in the previous series).
As representative selection examples, the TPS54331 (TI, 28V input support, 3A) and MP2315 (Monolithic Power Systems, 24V input, 3A) are often used in FC design.
Synchronous rectification converters have the advantage of higher efficiency and less heat generation than asynchronous types (diode rectification). In modern FC design, synchronous rectification is almost the standard.
The selection of the switching frequency is as explained in the EMI series; 500kHz or higher is common to avoid audible noise. Higher frequencies contribute to the miniaturization of inductors and capacitors, but there is a trade-off with increased switching losses and EMI (the same principle as the switching loss discussion in ESC12 applies here).
Power Sequencing
When there are multiple voltage rails, the design of the startup order (power sequence) is important.
In multi-voltage MCUs like the STM32H7, VCORE (core power) must rise before or at the same time as VDD (I/O power). The startup sequence requirements are clearly stated in the Power Supply Scheme section of the datasheet; violating this will prevent the MCU from starting normally or reduce long-term reliability.
The power sequence for sensor systems is also important. Some IMUs and GNSS modules have constraints on the rise time of VDD, which are controlled by a power sequencer IC or an RC timer circuit.
Methods for implementing power sequencing include using a dedicated sequencer IC (such as the TPS3808) or software-controlling the Enable pins of each LDO using the MCU's GPIO. The latter requires designing the initial stage of startup (ensuring the MCU power is brought up reliably by an independent circuit) because other power supplies cannot be started until the MCU's own power is stable.
Protection Circuit Design
Multiple protection mechanisms are required for the FC power input.
Reverse connection protection is implemented using an ideal diode (a low-loss backflow prevention circuit using a P-MOSFET) or a Schottky diode. While ideal diodes have a low voltage drop (tens of mV) and generate less heat, the circuit is somewhat more complex. Ideal diodes are standard for high-current FCs.
Overvoltage protection is implemented using a TVS diode. It protects the circuit from back-EMF when the motor starts and surges when the battery is connected. It is placed immediately after the VBAT line input, and the clamping voltage is set lower than the MOSFET breakdown voltage.
Overcurrent protection is implemented using a fuse or a polyswitch (self-resetting fuse). It limits current during a short circuit and prevents thermal destruction of the circuit.
The input filter is the pi-type filter explained in the EMI series. In configurations that share a battery with the motor power, it is essential to prevent switching noise from the motor side from entering the FC power system.
Preview of LDO vs. DC-DC Usage
An important decision in power design is choosing whether to use an LDO (linear regulator) or a DC-DC (switching regulator) for each voltage rail.
As a general guideline, DC-DC is essential for efficiency when the voltage difference is large and the current is high (e.g., VBAT to 5V). When the voltage difference is small and the current is low (e.g., 5V to 3.3V, for sensors), LDOs are advantageous in terms of noise characteristics.
These criteria and the details of each design will be covered in depth in the next installment, FC22.
Relationship Between Power Design and EMI
Power design is closely linked to the EMI countermeasures of the previous series.
The switching node of a DC-DC converter is the largest source of noise, as explained in the EMI series. At the power tree design stage, it is necessary to plan a layout that physically separates the DC-DC from sensors (especially GNSS and compasses).
The hierarchical structure of the power tree itself is a design for noise isolation. The core of power architecture design is the dual approach of electrically isolating noise-sensitive sensor power (LDO) from the noisy primary step-down stage (DC-DC) and further separating them physically in the layout.
The placement and capacitance selection of decoupling capacitors for each voltage rail will be covered in detail in FC23.
Verification Items for Power Supply Design
We will organize the items that should be confirmed once the power architecture design is complete.
In the power budget calculation, we sum the maximum current for each load and verify that there is a margin of at least 50% relative to the current rating of the primary step-down stage. We also consider instantaneous load fluctuations (such as sensor startup sequences, SD card writing, etc.).
In the voltage drop estimation, we calculate the voltage drop caused by wiring resistance. In large aircraft where the wiring from VBAT to the FC is long, the voltage drop due to wiring resistance can cause a decrease in the DC-DC input voltage, leading to dropout.
In the ripple current check, we verify that the output ripple of each DC-DC is below the allowable noise level of the loads (especially sensors).
In the preliminary thermal design calculation, we estimate the loss of each regulator (calculated from conversion efficiency) and the heat dissipation capacity of the PCB, setting the stage for the thermal design that will be covered in detail in FC29.
Summary
FC power supply design is structured in a hierarchy consisting of input protection, a primary step-down stage, and multiple independent LDO systems. The core is to electrically and physically separate the noisy high-current stages from the noise-sensitive sensor power supplies. Power sequencing is necessary to meet the startup requirements of multi-voltage MCUs and sensors, and three-layer protection—reverse connection protection, overvoltage protection, and overcurrent protection—is the foundation of reliability. Power supply design is two sides of the same coin as EMI countermeasures, and it is necessary to achieve overall optimization in conjunction with subsequent decoupling design and ground design. In the next session, FC22, we will explain LDOs and DC-DCs—comparing their characteristics and the selection criteria for using the right tool for the right job.