Last time, we compared communication protocols between FC and ESC. In this article, we will delve into the power system design of the ESC board. The reliability and efficiency of the inverter circuit are determined by a combination of three elements: not just the MOSFETs themselves, but also the input capacitors, gate drivers, and dead-time control. Since design errors lead directly to MOSFET destruction, careful understanding is required.
Why input capacitors are essential
The ESC input power is supplied by a battery, but there is parasitic inductance in the wiring connecting the battery and the ESC. The longer and thinner the power cable, the greater the inductance.
The moment the MOSFET switches, the current changes rapidly. When a current change dI/dt occurs in an inductance L, a voltage spike V = L × dI/dt is generated. In high-current ESCs where switching current is several tens of A and dI/dt reaches several A/ns, this spike can reach several tens of V or even over 100V in some cases, exceeding the MOSFET's breakdown voltage and destroying it.
The input capacitor is a buffer placed right at the ESC power input to absorb this spike. At the moment of switching, the capacitor supplies/absorbs charge, circulating current locally without going through the wiring inductance. This significantly suppresses voltage spikes.
Selection of input capacitors
The characteristics required for input capacitors are not just capacity. The most important metric is ESR (Equivalent Series Resistance). If the ESR is high, a voltage drop occurs due to the capacitor's internal resistance the moment a large current flows, weakening the spike suppression effect. Furthermore, the heat generated by ESR × I² causes the capacitor to degrade or fail.
Electrolytic capacitors are easy to obtain in large capacities, but they have high ESR and poor high-frequency characteristics. It is standard practice to choose low-ESR types (such as polymer aluminum electrolytic capacitors).
MLCC ceramic capacitors have extremely low ESR and excellent high-frequency characteristics, but large-capacity products generate mechanical vibration due to the piezoelectric effect. A standard configuration is to place MLCCs of several µF to several tens of µF in parallel with electrolytic capacitors to lower impedance over a wide band.
The following logic can be used for capacity selection. If the allowable voltage ripple is ΔV:
C ≥ I × Δt / ΔV
I is the peak value of the switching current, Δt is the switching time, and ΔV is the allowable ripple voltage. For drone ESCs, a combination of several hundred µF of electrolytic and several µF of MLCC is common.
Physical placement is also extremely important. Capacitors should be placed at the shortest distance between the MOSFET source and drain. If the wiring from the capacitor on the PCB to the MOSFET is long, the inductance of this wiring negates the capacitor's effect. Minimizing the area of the switching loop (Power → High-side MOSFET → Low-side MOSFET → GND → Capacitor → Power) is the core of the design.
The role of the gate driver
MOSFETs are turned on and off by the gate-source voltage Vgs. The MOSFET gate is capacitive (gate capacitance Cg), and this Cg must be charged and discharged to switch on and off.
Since an MCU's GPIO can only supply a few mA of current, it cannot directly drive high-power MOSFETs. A gate driver IC is a dedicated IC that receives logic signals from the MCU and charges/discharges the gate at high speed with a peak current of several A.
Main specifications of gate drivers:
The higher the peak current, the faster the switching, which reduces switching losses. Typical drone ESCs use gate drivers with peak currents of 2 to 4 A.
Propagation delay is the time from the input to the change in gate output, with devices in the range of several tens of ns being common. The difference in propagation delay (matching) between the high-side and low-side gate drivers affects dead-time design.
Half-bridge drivers are ICs that control both high-side and low-side gates as a single unit, and many have built-in dead-time generation functions. Representative examples include the IR2104, DRV8302, and MP6540.
The bootstrap circuit is a structure necessary for driving the high-side MOSFET. Since the source of the high-side MOSFET is connected to the output node (switching node) and its potential fluctuates, it cannot be driven with a fixed voltage. A method is widely adopted that uses a bootstrap capacitor (around 100 nF), which is charged while the low-side MOSFET is on, and that charge is used when driving the high-side.
A gate resistor is a resistor (several Ω to several tens of Ω) inserted in series between the gate driver and the MOSFET gate to adjust the switching speed. Reducing the resistance allows for high-speed switching and low loss, but steep dV/dt increases radiated noise. Increasing it slows down the switching and reduces noise, but increases switching loss. It is determined by the trade-off between EMC requirements and efficiency.
Dead-time control: Preventing shoot-through current
Each half-bridge in a three-phase bridge has a high-side MOSFET and a low-side MOSFET. If the low-side is turned on while the high-side is on, the power supply and GND are directly connected (shoot-through current, arm short-circuit), causing hundreds of amperes to flow instantly and destroying the MOSFETs.
To prevent this, a time margin (dead-time) is provided between turning one off and turning the other on. The dead-time is set in the range of several tens of ns to several µs.
If the dead-time is too short, the risk of shoot-through current remains. If it is too long, current flows through the freewheeling diode during the dead-time, causing voltage drop and loss (dead-time loss). In FOC control, where high efficiency is required, this loss is incorporated into the current control and corrected using a technique called dead-time compensation.
The turn-on and turn-off times of a MOSFET are determined by the gate capacitance and drive current, and even with the same MOSFET, they change depending on the gate driver settings. The dead-time is set by adding a sufficient margin to the switching time to ensure that no shoot-through occurs even under worst-case conditions (temperature, variations).
In actual design, the gate voltage waveforms of the upper and lower MOSFETs are observed simultaneously with an oscilloscope to verify through actual measurement that the dead-time is secured, the bootstrap voltage is sufficient, and the rise and fall of the gate waveforms are as designed.
Thermal design and MOSFET placement
The heat generated by MOSFETs handling large currents cannot be ignored. The sum of copper loss (I² × Rds(on)) and switching loss is generated as heat.
Since heat dissipation space is limited in small drone ESCs, models with extremely low Rds(on) are selected, and the copper foil of the PCB is used as a heat sink. A structure with wide copper foil on the motor pads and connecting the back pads of the MOSFETs to the GND plane via vias is standard.
The shunt resistor for current sensing is placed near the MOSFET for accurate current measurement. The shunt value is around several mΩ, and it must be kept at or below the level of Rds(on) to avoid increased loss.
Summary
ESC power system design consists of three elements: spike absorption by input capacitors, high-speed switching by gate drivers, and shoot-through prevention by dead-time control. Since design errors in each of these can lead directly to MOSFET destruction, understanding the theory and verification through actual measurement are essential. In PCB layout, minimizing the switching loop area is the most important factor, which is a principle shared with the EMI countermeasures of the previous series. Next time, I will explain ESC current sensing and feedback control—current loops and PID design.